It is well known by those skilled in the art that the electrical contact and structural stability of a cobalt silicide thin film in contact with a silicon substrate is critical for electrical conductivity and performance of semiconductor devices. It is also well known by those skilled in the art that the electrical contact and structural stability of a cobalt germanide thin film in contact with a germanium substrate is also critical. Therefore, a thin film of cobalt silicide or cobalt germanide which has enhanced resistance to structural degradation caused by thermal annealing is desirable.
Problems with cobalt silicide/silicon contact regions have been found when the cobalt silicide structure is exposed to high temperature annealing (over 750.degree. C.). Those skilled in the art have discovered that a low resistance cobalt silicide/silicon contact treated by heating over 750.degree. C. results in a contact in which the quality degrades because of the agglomeration and/or inversion Of the cobalt silicide and the silicon substrate, This causes open or high resistance interconnections, high contact resistances and electrical leakage which lead to device failure.
For example, as known to those skilled in the art, one aspect of current silicon technology utilizes ion implantation for the formation of source/drain junctions followed by the deposition of a thin cobalt film and thermal annealing at 600.degree. C. to 750.degree. C. to convert cobalt into cobalt silicide. After silicide formation, a high temperature thermal anneal is performed (&gt;750.degree. C.) to electronically activate the dopants in the source, gate and drain regions of the device. Low sheet resistance contacts and low leakage source and drain junctions are difficult to form by this technique because of the structural degradation of the cobalt silicide that occurs during the high temperature activation anneal.
One approach to solve these problems is to conduct the ion implantations and high temperature annealing steps (&gt;750.degree. C.) required for the source, gate and drain electrical activation before the deposition and formation of the cobalt silicide/silicon contact. However, further processing of the silicon device after silicide formation must be limited to temperatures below the formation temperature of the cobalt silicide in order to avoid agglomeration of the cobalt silicide and device degradation. These temperature limitations are often difficult to maintain for processing of integrated silicon circuits.
Yet another shortcoming with the known technology occurs because the silicon used for the cobalt silicide/silicon contact is polycrystalline silicon. This would be the situation in local interconnects for wiring transistors together or gate structures for CMOS, bipolar or ASIC circuits. Thin film cobalt silicide/polycrystalline silicon contacts have less structural stability under thermal stressing than cobalt silicide/single Crystal silicon structures. As a result, the thin film cobalt silicide/polycrystalline will agglomerate and invert with lower temperature anneals. As known to those skilled in the art, this problem is particularly acute in integrated schemes where the cobalt silicide/polycrystalline silicon gate contact is formed during the cobalt silicide/silicon source and drain formation and before high temperature dopant electronic activation anneals.
Some prior art designs provide alternate structures using silicide and silicon substrates. However, these designs fail to achieve a structure which can satisfy the above criteria for high temperature resistance of silicide to thermal agglomeration on a silicon substrate.